In practical data processing systems, the library of programs required for performance of the processes to be implemented is often quite large compared to the capacity of the processor's high speed main memory. The main memory capacity is limited by economical considerations since the cost of high speed random access memory is quite high in comparison to many types of sequential access mass memory, e.g., disks, tapes, etc. There is a continuing modification of the allocation of the main memory in the course of executing programs from the library. Accordingly, economical utilization of the main memory dictates dynamic relocation of main memory storage areas to the various programs that are required for execution. In a commonly used prior art arrangement, a table translator comprising one entry for each page of program or data stored in the main memory is maintained in an auxiliary random access memory. Each such entry in the table comprises one or more access control bits and associated data which comprises at least part of a main memory address. In this prior art arrangement, the control bit or bits and the associated data are stored in a word location of the auxiliary random access memory. When the table stored in the auxiliary memory is to be changed, each successive word in the memory must be altered. Most tables only require a small portion of the total capacity of the auxiliary memory since the memory is made sufficiently large to accommodate the largest tables allowable. Accordingly, it is theoretically possible to overwrite only those addresses which are required for the new table. However, since the associated program may generate erroneous table addresses, it is advisable to clear either all the control bits in the auxiliary memory or the entire memory before the new table is established. Unfortunately, to effect a change of the control bits alone or of the data alone in this prior art arrangement, it is necessary to address all auxiliary memory locations since the control bits are distributed over all auxiliary memory locations.